How Transistor Area Shrank by 1 Million Fold by Howard Tigelaar

Author:Howard Tigelaar
Language: eng
Format: epub
ISBN: 9783030400217
Publisher: Springer International Publishing

At the 180 nm technology node, polysilicon gate dummy geometries were added to assist gate photolithography and to provide a more planar surface post premetal dielectric (PMD) CMP for improved contact pattern depth of focus.

At the 130 nm node, dummy transistor gates were added next to isolated core transistor gates to improve transistor-to-transistor matching by assisting with printing the gates and minimizing etch loading effects.

Figure 9.27a–d illustrate the placement of dummy poly geometries in the layout of a transistor gate pattern.

Fig. 9.27(a) Gate pattern from design engineers, (b) dummy assist geometries generated by the dummy assist software program, (c) gate pattern plus dummy gate pattern before optical proximity corrections (OPC) are applied, (d) gate pattern after OPC and after dummy fill. This pattern is sent to the reticle shop

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