High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip by Zheng Wang & Anupam Chattopadhyay

Author:Zheng Wang & Anupam Chattopadhyay
Language: eng
Format: epub
Publisher: Springer Singapore, Singapore

5.1.4 Analytical Reliability Estimation for RISC Processor

In this section, the reliability analysis based on the proposed methodology is presented. First, the estimation of IER for individual operation is shown. In the next AER is calculated from IER and application dependent weights of instructions. The estimated values are compared with experimental values.

5.1.4.1 IER

A set of testbenches are developed to get individual . Each testbench contains the same type of instructions with different modes and random operands. The single bit-flip fault with duration 1 clock cycle targeting a specific operation is then injected during each simulation. Mismatches can be easily detected when both faulty and golden simulations are performed. Each operation specific is obtained from 3000 simulations. The IER can also be derived analytically from Eq. 5.1, where and need to be obtained based on fault simulations. Here the experimental value is simply applied for higher estimation accuracy.

Table 5.1 shows s of instruction as an example. Table 5.1 also shows the application dependent weights of instructions for Sobel. The weights are used to calculate , which constitutes one portion of the AER in Eq. 5.2. Such weights can be obtained directly by the profiling tools of Processor Designer. Note that and operations are subdivided into several modes. This is because different modes of the same instruction type have distinct IERs and weights. The IER among different modes is the weighted average of IERs for all modes.Table 5.1Instruction-level reliability estimation [216]

Copyright ©2013 IEEE

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