Hands-on Experience with Altera FPGA Development Boards by Jivan S. Parab Rajendra S. Gad & G. M. Naik

Author:Jivan S. Parab, Rajendra S. Gad & G. M. Naik
Language: eng
Format: epub
Publisher: Springer India, New Delhi

1:8 Demultiplexer Truth Table

Select inputs

Output (D out)

A

B

C

Dout (7)

Dout (6)

Dout (5)

Dout (4)

Dout (3)

Dout (2)

Dout (1)

Dout (0)

0

0

0

0

0

0

0

0

0

0

I

0

0

1

0

0

0

0

0

0

I

0

0

1

0

0

0

0

0

0

I

0

0

0

1

1

0

0

0

0

I

0

0

0

1

0

0

0

0

0

I

0

0

0

0

1

0

1

0

0

I

0

0

0

0

0

1

1

0

0

I

0

0

0

0

0

0

1

1

1

I

0

0

0

0

0

0

0

Procedure for Demux Implementation

Steps for creating the demultiplexer designs are same as that of multiplexer, and the design code for 1:8 demultiplexers is given below.

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